SH1106 seem to be a popular alternative to SSD1306 in many projects. And recompiling is not always an option or may be a lot of messing around when switching back and forth between OLED and VGA.
@Mr.Blinky figured how to hex between ssd1306 and ssd1309 so this one wouldn’t be an issue.
SSD1327 128x128 could provide some interesting results as could SSD1329 96x96
Difference between SSD1306 / SSD1309 is one of the configuration commands, and the FPGA code ignores all commands anyway and only listens for the data, so SSD1309 should work fine.
SH1106 - the issue here is that the page address does not automatically increment. So you need to manually set the page addresses during the frame… which means the DC pin is being toggled during the frame and this upsets the FPGA code!
I did write a temporary workaround for trying out the VGA1306 board with @Mr.Blinky’s streaming-bootloader demo, which uses this page-addressing mode for maximum SSD1306 / SH1106 cross-compatibility…
Just needed to replace this portion of Verilog:
always @(posedge wclk) // Write memory
begin
if (write_en) begin
mem[waddr] <= din; // Using write address bus
waddr_r <= waddr_r + 1; // Increment address
end
else begin
waddr_r <= 0; // 'VSYNC'
end
end
with this:
always @(posedge wclk) // Write memory
begin
if (write_en == 1 && waddr_r < 8192) begin
mem[waddr] <= din; // Using write address bus
waddr_r <= waddr_r + 1; // Increment address
end
else if (waddr_r == 8192) begin
waddr_r <= 0; // 'VSYNC'
end
end
So, yes - a ‘universal’ SSD1306 / SSD1309 / SH1106 version shouldn’t be difficult!
Could definitely be interesting, yes. 16 shades of grey to play with!
The current 3-bit RGB hardware only allows for 8 colours though 
But add another five resistors, and you get 256 colours! 
Thought I’d better reply to this over here… 
…if you remove the flash chip from the socket and use some other external device to send the initial configuration to the FPGA in ‘slave mode’, then the four SPI pins (SPI_SO, SPI_SI, SPI_SS_B and SPI_SCK) become available to the user application 49 clock cycles later - and that same external device can then take advantage of those IO!
Details are on page 26/27 of the iCE40 Programming and Configuration Technical Note.
(EDIT: SPI_SS_B and SPI_SCK do have pull-up resistors attached though, which may limit their usefulness! 
)
Hmm…I can tell 32 shades.
these many things make me think of my homemade bridge diode…
Or one of those mililtary circuit board(Fallout junk items) ancient circuit board with no less than 50 of them on board
Wait. it work with SSD1306? 
@Mr.Blinky
If you can give me the sketch for NES controller (for a Arduino Micro), and @uXe figure out how to get one of your board to be, then I might be able to fit all these onto one Proto-shield. With a 3.5mm headphone jack.
That being what I am aiming for, but @uXe’s board is a tad too big.
Have uploaded an ‘SH1106-friendly’ variation of the code - which listens out for the 0xB0 page-address command to achieve VSYNC, instead of relying on the DC pin:
Somebody was going to throw away a display that had VGA! so finally I was able to test the board
https://photos.app.goo.gl/2UnoG9BC78zbSLZd8
Thanks a lot @uXe works like a charm and makes me again to want to learn FPGAs 
Great choice of game for your first run!
Probably also time to clean the desk.
Ignore @filmote, please don’t ever clean your desk, a good programmer’s desk should be messy :P
That’s funny to hear from someone known to clean up codes all the time :P
Bammmmm !
Clean code, messy desk - it’s like the ‘cold hands, warm heart’ thing. :P
My code is clean because I’ve worked out how to make it clean by designing it with the bits of paper strewn across my desk. :P
(P.S. ‘code’ is uncountable when used in a programming context.)
Rather than cleaning I think I need a motorized double-decker desk. That would be awesome. Also it is not messy, I know where is everything.
Sure … everything is on the desk.
hahah awesome answer. I am going to use that one-liner now in my daily life
WOOT! 
Then you will be happy to know I spent today exploring the use of the VGA1306 board as a stand-alone FPGA gaming device! 
Re-assigned the four input pins to be used as inputs for four directional buttons tied to pull-up resistors (using a resistor array in a DIP package here):
Here’s the Verilog… now get learnin’! 
What is the 8 pin IC? Is there another AVR CPU on here we’re actually talking with that’s then talking to the Lattice chip?
The 8-pin IC is an SPI Flash memory chip - the specific one I used here is a A25L080. The FPGA automatically reads the ‘firmware’ from the flash chip and configures itself every time at power-up.
Basically, you just externally reflash that chip to load new firmware - or you can also pull the chip from the socket altogether and use the SPI pins that are exposed on that 8-pin footprint (plus RESET & DONE on the separate 2-pin header) to directly upload new firmware instead using a microcontroller (needs to be 3.3V!) or a Raspberry Pi for example…
Good explanation that helped me make sense of it here:
What is all the boilerplate code at the end? IE:
if(c_col == 639 && c_row == 84) begin
raddr_temp <= 6;
end
That’s just my hacky way of dealing with the way the Arduboy screen buffer is formatted, and scaling it up from 128x64 to 640x320! 
There is likely a more elegant way to do it - but it works / it ain’t broke… 
I get that, but what is it actually doing? What is raddr_temp for?