VGA1306 (VGA-out for DIY Arduboys implemented on an FPGA!)

Hi uXe, any chance you could PM me? I’ve been experimenting with a DE0 nano using the Quartus ii software, I’m using their mega functions to create a PLL clock for the 25 MHz pixel clock input.

I am using this to output video from the DMG and have it mostly working, there are just some weird issues that I’m not really sure how to troubleshoot.

Would be awesome if you could help me with this.

PM’d :slight_smile:

I really like Chris’ user id ! @0xcf … unfortunately my name doesn’t allow that :frowning:


@filmote its probably the only cool thing about my name, at least when you talk to someone you can always use the line "Simon says… " :slight_smile:

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… which is better than them getting in first with ‘simple simon’.